Pull-up resistor calculator

Output

IC

IC producing an open-drain output

Pin

Pin carrying the open-drain output

$$I_{LKG(max)}$$

Leakage current (max)

$$V_{OL(max)}$$

Logic-low voltage (max)

$$I_{OL(max)}$$

Test current for $$V_{OL(max)}$$

Input supply

$$V_{min}$$

Supply voltage (min)

$$V_{max}$$

Supply voltage (max)

Input

IC

IC expecting a push-pull input

Pin

Pin receiving the push-pull input

$$V_{IL(max)}$$

Logic-low voltage (max)

$$V_{IH(min)}$$

Logic-high voltage (min)

$$I_{IN(max)}$$

Input bias current (max)

Pull-up resistor

$$R_{pull-up(min)}$$

Resistance (min)

Exact
$$V_{IL(max)}$$ value required
$$I_{OL(max)}$$ value required
$$V_{max}$$ value required
$$V_{OL(max)}$$ value required
$$V_{OL(max)}$$ must not exceed $$V_{IL(max)}$$
$$I_{IN(max)}$$ value required
Standard

$$R_{pull-up(max)}$$

Resistance (max)

Exact
$$V_{min}$$ value required
$$V_{IH(min)}$$ value required
$$I_{LKG(max)}$$ value required
$$I_{IN(max)}$$ value required
Standard

Discussion

This discussion assumes you are familiar with the general principles behind pull-up resistors.

The circuit being analyzed has two sides. The output side outputs an open-drain logic state, and the input side receives a push-pull logic state. The pull-up resistor must meet two criteria:

• When output is logic-high, and therefore in high impedance state, signal voltage has to exceed minimum logic-high voltage of input
• When output is logic-low, and therefore tied to ground, signal voltage must not exceed maximum logic-low voltage of input or output

Logic-high

In the first case (logic-high), the supply is sourcing current, output is leaking some current to ground, and the rest of the current is going to input:

The lowest value of $$V_{signal}$$ occurs when supply power is at a minimum, and the two currents are at a maximum; in order for the circuit to function properly, this value of $$V_{signal}$$ must exceed the minimum logic-high voltage of input, $$V_{IH(min,input)}$$.

Component parameters that determine viable values of the pull-up resistor are:

• Minimum supply voltage $$V_{supply(min)}$$
• Maximum current on output in logic-high state, also known as open-drain leakage current $$I_{LKG(max,output)}$$
• Maximum current on input $$I_{IN(max,input)}$$
• Minimum input logic-high voltage $$V_{IH(min,input)}$$

\begin{aligned} V_{signal} & \ge V_{supply(min)} - R_{pull-up} (I_{LKG(max,output)} + I_{IN(max,input)}) \ge V_{IH(min,input)} \\ \Rightarrow R_{pull-up} & \le {{V_{supply(min)} - V_{IH(min,input)}} \over {I_{LKG(max,output)} + I_{IN(max,input)}}} = R_{pull-up(max)} \end{aligned}

Logic-low

In the second case (logic low), the supply is sourcing current, output is sinking this current to ground, and input is leaking some current, which output is also sinking to ground:

Signal voltage $$V_{signal}$$ is related to the current sunk by output; the relationship between the two may not be linear, but it is monotonic, so that increasing current sunk by output also increases signal voltage.

$$V_{signal}$$ is required to remain below the maximum logic-low voltage for output, $$V_{OL(max)}$$. That also means that current sunk by output must remain below the current that would produce $$V_{OL(max)}$$. This current, $$I_{OL(max)}$$, can be found in datasheets as the test current for $$V_{OL(max)}$$.

The highest value of $$I_{OL(max)}$$ occurs when supply voltage is at a maximum, signal voltage is at a mimimum, and input leakage current is at a maximum.

Signal voltage minimum is zero; other component parameters that determine viable values of the pull-up resistor are:

• Maximum supply voltage $$V_{supply(max)}$$
• Maximum current on input, also known as bias current $$I_{IN(max,input)}$$
• Maximum output logic-low current $$I_{OL(max,output)}$$

Therefore:

\begin{aligned} I_{output} & \le {{V_{supply(max)} - V_{signal(min)}} \over R_{pull-up}} + I_{IN(max,output)} \le I_{OL(max,input)} \\ \Rightarrow R_{pull-up} & \ge {{V_{supply(max)}} \over {I_{OL(max,input)} - I_{IN(max,output)}}} = R_{pull-up(min)} \end{aligned}

Additionally, $$V_{signal}$$ is required to remain below the maximum logic-low voltage for input. If this voltage exceeds the maximum logic-low voltage for output, then this requirement is automatically satisfied when $$R_{pull-up} \ge R_{pull-up(min)}$$.

However, since the relationship between output sink current and signal voltage is generally unknown, when maximum logic-low voltage for input is below the maximum logic-low voltage for output, there is no definitive way to calculate the range of viable pull-up resistors. The only option is to err on the side of larger pull-up resistor values.

Acknowledgements

This calculator and the discussion are based on information from TI Application Report SLVA485 by Ben Hopf.

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